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ICS858020
LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-CML FANOUT BUFFER
GENERAL DESCRIPTION
The ICS858020 is a high speed 1-to-4 Differentialto-CML Fanout Buffer and is a member of the HiPerClockSTM HiPerClockSTM family of high performance clock solutions from ICS. The ICS858020 is optimized for high speed and very low output skew, making it suitable for use in demanding applications such as SONET, 1 Gigabit and 10 Gigabit Ethernet, and Fibre Channel. The internally terminated differential input and VREF_AC pin allow other differential signal families such as LVDS, LVHSTL and CML to be easily interfaced to the input with minimal use of external components. The ICS858020 is packaged in a small 3mm x 3mm 16-pin VFQFN package which makes it ideal for use in space-constrained applications.
FEATURES
* Four differential CML outputs * One LVPECL differential clock input * IN, nIN pair can accept the following differential input levels: LVPECL, LVDS, CML, SSTL * Maximum output frequency: 3.2GHz * Output skew: 30ps (maximum) * Part-to-part skew: 225ps (maximum) * Additive phase jitter, RMS: <0.03ps (typical) * Propagation delay: 600ps (maximum) * Operating voltage supply range: VCC = 2.375V to 3.63V, VEE = 0V * -40C to 85C ambient operating temperature * Available in both standard (RoHS5) and lead-free (RoHS 6) packages
IC S
BLOCK DIAGRAM
PIN ASSIGNMENT
nQ0
IN 1 VT 2 Q0 nQ0 VREF_AC 3 nIN 4
16 15 14 13 12 11 10 9 5
VEE
VCC
VEE
Q0
Q1 nQ1 Q2 nQ2
nQ3
Q1 nQ1 VREF_AC Q2 nQ2
ICS858020
16-Lead VFQFN 3mm x 3mm x 0.95 package body K Package Top View
Q3 nQ3
858020AK
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VCC
Q3
IN VT nIN
6
7
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ICS858020
LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-CML FANOUT BUFFER
TABLE 1. PIN DESCRIPTIONS
Number 1 2 3 4 5, 16 6, 7 8, 13 9, 10 11, 12 14, 15 Name IN VT VREF_AC nIN VEE nQ3, Q3 VCC nQ2, Q2 nQ1, Q1 nQ0, Q0 Input Input Output Input Power Output Power Output Output Output Type Description Non-inver ting LVPECL differential clock input. This input internally terminates with 50 to the VT pin. Termination input. Reference voltage for AC-coupled applications. This output biases to VCC - 1.38V. Inver ting differential LVPECL clock input. This input internally terminates with 50 to the VT pin. Negative supply pin. Differential output pair. CML interface levels. Positive supply pins. Differential output pair. CML interface levels. Differential output pair. CML interface levels. Differential output pair. CML interface levels.
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LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-CML FANOUT BUFFER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC Inputs, VI Outputs, IO Continuous Current Surge Current Input Current, IN, nIN VT Current, IVT Input Sink/Source, IREF_AC Storage Temperature, TSTG Package Thermal Impedance, JA
(Junction-to-Ambient)
4.6V (CML mode, VEE = 0) -0.5V to VCC + 0.5 V 20mA 40mA 50mA 100mA 0.5mA -65C to 150C 51.5C/W (0 lfpm)
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Operating Temperature Range, TA -40C to +85C
TABLE 2A. POWER SUPPLY DC CHARACTERISTICS, VCC = 2.375V TO 3.6V; VEE = 0V
Symbol VCC IEE Parameter Positive Supply Voltage Power Supply Current Test Conditions Minimum 2.375 Typical 3.3 Maximum 3.6 135 Units V mA
TABLE 2B. DC CHARACTERISTICS, VCC = 2.375V TO 3.6V; VEE = 0V
Symbol RIN VIH VIL VIN VDIFF_IN VREF_AC VT_IN Parameter Differential Input Resistance Input High Voltage Input Low Voltage Input Voltage Swing; NOTE 1 Differential Input Voltage Swing Reference Voltage In-to-VT Voltage (IN, nIN) (IN, nIN) (IN, nIN) Test Conditions IN to VT Minimum 40 1.2 0 0.15 0.3 VCC - 1.5 VCC - 1.4 Typical 50 Maximum 60 VCC VIH - 0.15 2.8 3.4 VCC - 1.3 1.5 Units V V V V V V
NOTE 1: Refer to Parameter Measurement Information, Input Voltage Swing diagram.
TABLE 2C. CML DC CHARACTERISTICS, VCC = 2.375V TO 3.6V; VEE = 0V
Symbol VOH VOUT VDIFF_OUT ROUT Parameter Output High Voltage; NOTE 1 Output Voltage Swing Differential Output Voltage Swing Output Source Impedance Conditions Minimum VCC - 0.020 325 650 40 Typical VCC - 0.010 400 800 50 60 Maximum VCC Units V mV mV
NOTE 1: Outputs terminated with 100 across differential output pair.
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TABLE 3. AC CHARACTERISTICS, VCC = 0V; VEE = -3.6V TO -2.375V OR VCC = 2.375 TO 3.6V; VEE = 0V
Symbol fMAX t PD tsk(o) tsk(pp) tjit tR/tF Parameter Maximum Output Frequency Propagation Delay; (Differential); NOTE 1 Output Skew; NOTE 2, 4 Par t-to-Par t Skew; NOTE 3, 4 Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter section Output Rise/Fall Time 20% to 80% 60 Condition Minimum Typical Maximum 3.2 350 15 575 30 225 <0.03 180 Units GHz ps ps ps ps ps
All parameters characterized at 1.2GHz unless otherwise noted. RL = 100 after each output pair. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
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ADDITIVE PHASE JITTER
The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in
0 -10 -20 -30 -40 -50
the 1Hz band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot.
Additive Phase Jitter at 155.52MHz = <0.03ps (typical)
SSB PHASE NOISE dBc/HZ
-60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 1k 10k 100k 1M 10M 100M
OFFSET FROM CARRIER FREQUENCY (HZ)
As with most timing specifications, phase noise measurements have issues. The primary issue relates to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the device. This is illustrated above. The de-
vice meets the noise floor of what is shown, but can actually be lower. The phase noise is dependant on the input source and measurement equipment.
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LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-CML FANOUT BUFFER PARAMETER MEASUREMENT INFORMATION
VCC
0V Qx
SCOPE
VCC CML Driver VEE
Power Supply
nIN
V
IN
Cross Points
V
IH
IN
V
IL
-3.3V 10% -2.5V 5%
V EE
OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
nQx PART 1 Qx nQy PART 2 Qy
tsk(pp)
nQx Qx nQy Qy
tsk(o)
PART-TO-PART SKEW
nIN IN nQ0:nQ3 Q0:Q3
tPD
OUTPUT SKEW
VIN VIN, VOUT 400mV (typical)
VDIF_IN VDIFF_IN, VDIFF_OUT 800mV (typical)
PROPAGATION DELAY
SINGLE ENDED & DIFFERENTIAL INPUT VOLTAGE SWING
80% Clock Outputs
80% VSW I N G
20% tR tF
20%
OUTPUT RISE/FALL TIME
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LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-CML FANOUT BUFFER APPLICATION INFORMATION
LVPECL INPUT
WITH
BUILT-IN 50 TERMINATION INTERFACE (2.5V)
by the most common driver types. The input interfaces suggested here are examples only. If the driver is from another vendor, use the termination they recommend. Please consult with the vendor of the driver component to confirm the driver termination requirements.
2.5V 2.5V
The IN/nIN with built-in 50 terminations accepts LVDS, LVPECL, LVHSTL, CML, SSTL and other differential signals. Both VSWING and VOH must meet the VIH and VIL input requirements. Figures 1A to 1D show interface examples for the HiPerClockS IN/nIN input with built-in 50 terminations driven
3.3V or 2.5V 2.5V
Zo = 50 Ohm IN Zo = 50 Ohm LVDS VT nIN
Zo = 50 Ohm IN Zo = 50 Ohm VT nIN 2.5V LVPECL R1 18
Receiver With Built-In 50 Ohm
Receiver With Built-In 50 Ohm
FIGURE 1A. HIPERCLOCKS IN/nIN INPUT WITH BUILT-IN 50 DRIVEN BY AN LVDS DRIVER
2.5V 2.5V
FIGURE 1B. HIPERCLOCKS IN/nIN INPUT WITH BUILT-IN 50 DRIVEN BY AN LVPECL DRIVER
2.5V 2.5V
Zo = 50 Ohm IN Zo = 50 Ohm VT nIN CML - Open Collector
Zo = 50 Ohm IN Zo = 50 Ohm VT nIN CML - Built-in 50 Ohm Pull-up
Receiver With Built-In 50 Ohm
Receiver With Built-In 50 Ohm
FIGURE 1C. HIPERCLOCKS IN/nIN INPUT WITH BUILT-IN 50 DRIVEN BY AN OPEN COLLECTOR CML DRIVER
FIGURE 1D. HIPERCLOCKS IN/nIN INPUT WITH BUILT-IN 50 DRIVEN BY A CML DRIVER WITH BUILT-IN 50 PULLUP
2.5V R1 25 Zo = 50 Ohm IN Zo = 50 Ohm R2 25 VT nIN
2.5V
SSTL
Receiver With Built-In 50
FIGURE 1E. HIPERCLOCKS IN/nIN INPUT WITH BUILT-IN 50 DRIVEN BY AN SSTL DRIVER
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LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-CML FANOUT BUFFER
LVPECL INPUT WITH BUILT-IN 50 TERMINATION INTERFACE (3.3V)
The IN /nIN with built-in 50 terminations accepts LVDS, LVPECL, LVHSTL, CML, SSTL and other differential signals. Both VSWING and VOH must meet the VIH and VIL input requirements. Figures 2A to 2D show interface examples for the HiPerClockS IN/nIN input with built-in 50 terminations driven by the most common driver types. The input interfaces suggested here are examples only. If the driver is from another vendor, use the termination they recommend. Please consult with the vendor of the driver component to confirm the driver termination requirements.
3.3V
3.3V
3.3V
3.3V
Zo = 50 Ohm IN Zo = 50 Ohm LVDS VT nIN
Zo = 50 Ohm IN Zo = 50 Ohm VT nIN LVPECL R1 50
Receiver With Built-In 50 Ohm
Receiver With Built-In 50 Ohm
FIGURE 2A. HIPERCLOCKS IN/nIN INPUT WITH BUILT-IN 50 DRIVEN BY AN LVDS DRIVER
FIGURE 2B. HIPERCLOCKS IN/nIN INPUT WITH BUILT-IN 50 DRIVEN BY AN LVPECL DRIVER
3.3V
3.3V
3.3V
3.3V
Zo = 50 Ohm IN Zo = 50 Ohm VT nIN CML- Open Collector
Zo = 50 Ohm IN Zo = 50 Ohm VT nIN CML- Built-in 50 Ohm Pull-Up
Receiver With Built-In 50 Ohm
Receiver With Built-In 50 Ohm
FIGURE 2C. HIPERCLOCKS IN/nIN INPUT WITH BUILT-IN 50 DRIVEN BY A CML DRIVER WITH OPEN COLLECTOR
FIGURE 2D. HIPERCLOCKS IN/nIN INPUT WITH BUILT-IN 50 DRIVEN BY A CML DRIVER WITH BUILT-IN 50 PULLUP
3.3V
3.3V
R1
25
Zo = 50 Ohm IN Zo = 50 Ohm VT nIN
SSTL
R2
25
Receiver With Built-In 50 Ohm
FIGURE 2E. HIPERCLOCKS IN/nIN INPUT WITH BUILT-IN 50 DRIVEN BY AN SSTL DRIVER
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SCHEMATIC EXAMPLE
Figure 3 shows a schematic example of the ICS858020. This schematic provides examples of input and output handling. The ICS858020 input has built-in 50 termination resistors. The input can directly accept various types of differential signal without AC couple. If AC couple termination is used, the ICS858020 also provides VREF_AC pin for proper offset level after the AC couple. This example shows the ICS858020 input driven by a 2.5V LVPECL driver with AC couple. The ICS858020 outputs are CML driver with built-in 50 pull up resistors. In this example, we assume the traces are long transmission line and the receiver is high input impedance without built-in matched load. An external 100 resistor across the receiver input is required.
3.3V
Zo = 50 + R3 100
Zo = 50 3.3V C1 0.1u 16 15 14 13
-
2.5V LVPECL Zo = 50 C5 1 2 3 4 C6 R1 100 R2 100 IN VT VREF_AC nIN
VEE Q0 nQ0 VCC
U1 ICS858020
100 Ohm Dif f erential
Zo = 50
Q1 nQ1 Q2 nQ2 VEE nQ3 Q3 VCC
12 11 10 9
3.3V 3.3V C2 0.1u Zo = 50 + Zo = 50 R4 100 100 Ohm Dif f erential
FIGURE 3. ICS858020 APPLICATION SCHEMATIC EXAMPLE
5 6 7 8
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VFQFN EPAD THERMAL RELEASE PATH
In order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the Printed Circuit Board (PCB) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in Figure 4. The solderable area on the PCB, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/ electrical performance. Sufficient clearance should be designed on the PCB between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. While the land pattern on the PCB provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are necessary to effectively conduct from the surface of the PCB to the ground plane(s). The land pattern must be connected to ground through these vias. The vias act as "heat pipes". The number of vias (i.e. "heat pipes") are application specific and dependent upon the package power dissipation as well as electrical conductivity requirements. Thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. Maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. It is recommended to use as many vias connected to ground as possible. It is also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/slug and the thermal land. Precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. Note: These recommendations are to be used as a guideline only. For further information, refer to the Application Note on the Surface Mount Assembly of Amkor's Thermally/Electrically Enhance Leadfame Base Package, Amkor Technology.
PIN
SOLDER
EXPOSED HEAT SLUG
SOLDER
PIN
PIN PAD
GROUND PLANE THERMAL VIA
LAND PATTERN (GROUND PAD)
PIN PAD
FIGURE 4. P.C.ASSEMBLY FOR EXPOSED PAD THERMAL RELEASE PATH -SIDE VIEW (DRAWING NOT TO SCALE)
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LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-CML FANOUT BUFFER RELIABILITY INFORMATION
TABLE 4. JAVS. AIR FLOW TABLE
FOR
16 LEAD VFQFN
JA at 0 Air Flow (Linear Feet per Minute)
0 51.5C/W
Multi-Layer PCB, JEDEC Standard Test Boards
TRANSISTOR COUNT
The transistor count for ICS858020 is: 28 Pin compatible with SY58020U
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PACKAGE OUTLINE - K SUFFIX FOR 16 LEAD VFQFN
(Ref.)
Seating Plane Index Area N Anvil Singula tion A1 A3 L
(ND-1)x e
(R ef.)
ND & NE Even N 1 2
e (Typ.) 2 If ND & NE
are Even (NE -1)x e
OR
Top View
E2
E2 2
(Re f.)
b A D Chamfer 4x 0.6 x 0.6 max OPTIONAL 0. 08 C C
(Ref.)
e D2 2 D2
ND & NE Odd
Thermal Base
TABLE 5. PACKAGE DIMENSIONS
JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS SYMBOL N A A1 A3 b e ND NE D D2 E E2 L 0.25 0.30 0.25 3.0 1.25 0.50 0.18 0.50 BASIC 4 4 3.0 1.25 0.80 0 0.25 Reference 0.30 MINIMUM 16 1.0 0.05 MAXIMUM
Reference Document: JEDEC Publication 95, MO-220
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TABLE 6. ORDERING INFORMATION
Part/Order Number ICS858020AK ICS858020AKT ICS858020AKLF ICS858020AKLFT Marking 020A 020A 20AL 20AL Package 16 Lead VFQFN 16 Lead VFQFN 16 Lead "Lead-Free" VFQFN 16 Lead "Lead-Free" VFQFN Shipping Packaging Tube 2500 Tape & Reel Tube 2500 Tape & Reel Temperature -40C to 85C -40C to 85C -40C to 85C -40C to 85C
NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. 858020AK
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REVISION HISTORY SHEET Rev A A A T6 Table T6 T6 Page 12 12 10 12 13 Description of Change Ordering Information Table - correct Shipping Packaging from Tray to Tube. Ordering Information Table - corrected marking from 820A to 020A. Added VFQFN EPAD Thermal Release Path section. Updated VFQFN package outline. Ordering Information Table - added Lead-Free marking. Date
3/17/06 4/24/06
12/10/07
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